As is known by one skilled in the art dies must be tested before being integrated with electronic equipment. For practical reasons they are tested when they still belong to their wafer, i.e. before they are separated from one another by a cut-off process along scribe lanes (or lines) defined therebetween.
Each die comprises internal pads allowing connection for wafer tests through the needles of a probe card and for the final application (e.g. wire bonding in a package). Sometimes one or more internal (test) circuits are added to the die to facilitate the wafer testing.
The dies may be tested one after the other by means of a probe card controlled by automated test equipment (ATE) and comprising needles for contacting some of their pads to provide their test circuits and some of their integrated components with test values of voltage or current or to collect the voltage or current they output. In this case the wafer is mechanically moved relative to a probe card for each of its dies to be tested. The time for moving the wafer from a die to a neighboring one takes typically 0.8 second, which is not negligible compare to the time required for testing one die. So this method of testing wastes a lot of time when the wafer comprises numerous dies, which is generally the case.
In order to reduce the wasted time and the number of tests carried out on a wafer it is also possible to test several dies in parallel. But this requires more automated test equipment (ATE) resources and a more complex probe card with much more contact needles, which induces mechanical issues and increases the probability of damaging the pads.
In other respects, and as mentioned before, a pad has a wafer testing function and a wire soldering (or alternatively bumping) function. Requirements for implementing these two functions are difficult to meet, notably because needles used for test connection have a mechanical impact which makes soldering more difficult. Moreover, wafer testing requires pads with a greater size than the one required for soldering size. Therefore, the die size is increased because of the wafer tests. Moreover, with all external circuitry that allows wafer testing, such as decoupling capacitors, loop filters, radio frequency (RF) probes, which are located on the probe card which is behind the connection needles, the wire parasitic associated with the needles reduces the ability of testing at high frequencies.